1. Technical Field
This invention relates in general to communication systems and information and data processing systems, and more particularly, to digital clock frequency multiplication and data serialization techniques for converting a stream of Q parallel data bits into serial data for transmission and/or processing.
2. Description of the Prior Art
In optical fiber transmission systems the trend is to increase the data rate further to exploit the high transmission capacity of single-mode optical fibers. The limiting factor for data rate increases is usually not the optical fiber data carrying capability, but rather electronic circuit performance. In digital communication networks, such as fiber optic transmission systems, parallel data bits must be converted into a serial data stream at the transmitting end for transfer to a remote receiving end. Conversion of parallel data to serial data conventionally requires frequency multiplication of the parallel data clock. This is typically accomplished by a phase locked loop (PLL), which is an analog component well known in the art. Data serialization is normally accomplished via a special circuit called a serializer. The PLL and serializer are considered to be critical components of the data communication network. These circuits traditionally operate at the serial data stream rate and usually limit communication channel data carrying capability.
A conventional frequency multiplication and data serialization circuit, generally denoted 10, is depicted in FIG. 1. Circuit 10 receives the parallel data clock (low frequency clock) on line 11 which is coupled to a PLL circuit 12. PLL 12 multiplies the parallel clock frequency and outputs on line 13 a serial data clock (high frequency clock) that is phase synchronized with the parallel data clock. The high frequency clock output of PLL 12 is input to a ring counter 14 and the clock "C" input of a data latch 18. Ring counter 14 produces Q synchronized pulses CLC(1), CLC(2), . . . , CLC(Q), wherein Q equals the number of parallel data bits. These synchronized pulses are output from counter 14 on respective lines 15 to a data selector 16, which uses the pulses as clocks for the parallel data bits which are input to data selector 16 on lines 17. A clock pulse on a line 15 causes a corresponding data bit on a line 17 to be transferred from a parallel data latch in selector 16 to the serial output stream on line 19. Line 19 is coupled to the data "D" input of latch 18, which again is clocked by the serial data clock from the PLL 12.
A phase locked loop typically includes a voltage controlled oscillator, phase detector, charge pump and filter. The voltage controlled oscillator's frequency is normally susceptible to noise, which manifests itself as jitter at the PLL output. Serial data jitter obviously degrades optical link performance and is therefore undesirable. With conventional technology difficulties are experienced in maintaining PLL jitter low in a noisy system environment. In addition, the ring counter and data select circuit of the prior art serializer of FIG. 1 consist of a large number of latches which must operate at a high frequency. These components therefore further limit the maximum serial data rate for a particular technology. Also, because of the large number of circuits required, power consumption makes large scale integration difficult.
The present invention, therefore, is designed to address the performance limitations of conventional frequency multiplication and data serialization technology, and thus allow for higher data rate signal processing for a given technology.